In our previous blog, we discussed the basics of quartz crystal and aspects of the oscillator design (you can find the blog here). However, in this blog, we will focus on the PCB layout of the crystal oscillator and the good practices.
The parameters for the crystal choice were outlined in our previous blog. Now that we have several crystal candidates, it’s time to consider the crystal package.
In space-constrained applications, the crystal package will often be dictated by the mechanical requirements. If we are constrained with one crystal package, we will most likely be able to find a crystal alternative part number (which is especially important in these times of supply chain unpredictability and shortage). There are approximately a dozen common crystal packages. Some of them are HC-49 (2 pin), 1.2×1.6 mm, 2×1.6 mm, 2×2.5 mm, 3.2×2.5 mm (all 4 pin) etc.
In the spirit of design industrialization (if our PCB real-estate situation allows us), we can benefit from the hybrid crystal footprint. This will broaden the alternative parts list. The example of such footprint can be seen in the figure below.
Figure 1. Hybrid crystal footprint
Crystal Oscillator General PCB Layout Guidelines
We will outline the general crystal oscillator PCB layout guidelines. All of these guidelines have a good intention, however not all of them are equally important in every case. That’s why we will discuss two design cases.
- Place all oscillator components as close as possible to the oscillator IC pins.
- Keep the load capacitors and series resistor as close as possible to the crystal.
- Keep high frequency (and fast rise time) components as far away as possible to the oscillator to avoid capacitive coupling.
- Keep the oscillator traces as short and straight as possible. This will reduce the chance of coupling.
- Keep the area under the crystal well-grounded.
- The ground connection for the load capacitors should be short and avoid the return currents from the fast communication interfaces.
- In case you use a single layer PCB, place the GND guard ring around all oscillator components and oscillator GND pin.
- Place oscillator as far as possible from potential heat sources (power components, RF transmitters…)
Digital System Oscillator Layout
In the majority of digital systems, the frequency accuracy and stability requirements are in the range of 10s of ppm. For this purpose, the nice simple and clean crystal, load capacitors and resistor placement will do the job perfectly fine. Simply lay them out as close as possible to the oscillator IC pins (same PCB side as the IC, e.g. top side), stitch the GND vias, and pour the bottom side (or the first internal layer) in a nice solid GND.
In most of the cases, there is no need for any GND isolations. If you are on a two-layer PCB, route the analog sensitive traces away from this region, as well as the digital aggressors (follow the above guidelines 1 to 6). If you are on a multi-layer PCB, simply ensure you have a clean GND plane between the oscillator and other traces.
Narrowband RF System Oscillator Layout
On the other hand, if you are designing a narrowband RF system (such as Sigfox or LoRa), where transmission lasts for a second or two and bandwidth is measured in 10s or 100s of Hz, you will want to take an additional measure.
The failure mechanism – the transmitter transmits the RF data and heats for a couple (not much) of degrees C. This heat is transferred to the crystal (which you have laid out compactly by following the above guidelines) and the crystal frequency drifts away. Of course, the RF system frequency source is the oscillator, so the transmitter frequency also drifts away. In these systems, if the oscillator frequency drifts only 10 ppm away, we will go out of the band and the communication will fail.
Bottom line – in this case, we need to approach differently to the oscillator design. The picture below is worth a thousand words
The oscillator is placed far away from the IC pins in order to ensure thermal decoupling. Also, since the greatest thermal conductor on a PCB is copper, there is a slot to prevent the heat to the surface near the oscillator. Besides that, the thermal capacitance of the oscillator itself has been increased by increasing the ground pour surface and thermal vias stitching.
In other words, the main objective of this design was to increase the thermal capacitance of the oscillator and to decouple it from the heat source (RF transceiver IC).
Always consider all the aspects of your design before approaching the oscillator layout.
In the next part of the series, we will discuss the crystal oscillator validation procedure. Stay tuned!